Static Random Access Memory (SRAM) devices have sensitive circuitry and often operate with high switching activity and at high temperature. This makes the transistors that make up their bitcells particularly vulnerable to various aging mechanisms including Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) degradation. NBTI and PBTI change transistor threshold voltages (VTH) over time and are major reliability concerns in modern system on a chip (SoC) designs. Since such aging effects can degrade critical robustness and performance metrics, such as data retention voltage (DRV) and read access time (TACC), it is highly desirable to provide mechanism to enable monitoring and managing aging effects upon memory devices.